Accelerating Radiation-Hardened Chip Development with JRC’s LEAP Standard Cell Library

Introduction

Sec 1

A government agency’s development of a High Performance Space Computer (HPSC) provides a high-profile example. Initially, the HPSC designers attempted to use PDSOI and FDSOI process nodes and failed to meet both radiation hardness and electrical performance requirements. Then the HPSC program pursued TMR with commercial libraries.

After years of development delays, rising costs, and persistent program risk, they shifted to JRC’s patented LEAP Standard Cell Library at the 12nm FinFET process node. The move significantly improved design efficiency, radiation resilience, and program viability. This allowed them to deliver a chiplet-based, radiation-hardened, 10-core, RISC-V® processor. This technology will offer 100 times the processing speed of anything on orbit today and incorporates artificial intelligence and machine learning capabilities for edge computing, enabling real-time information on orbit for split-second decision-making.

Challenges with TMR at Advanced Semiconductor Technology Nodes on Commercial Standard Cells

Radiation Weakness

Standard commercial cells are too sensitive to radiation effects to be used without radiation hardening measures.

As process nodes shrink (FinFET at 12nm, and soon GAA at sub-3nm) and logic chips become more complex, larger and more capable, the number of bits (on a single chip) that can be upset increases.

Spatial Redundancy

At advanced technology nodes the feature sizes are so small that one single event affects very many individual transistors. This means that RHBD relying on spatial redundancy either becomes very ineffective or very difficult to realize. 

For TMR all three redundant parts of the circuit must be separated from each other, possibly leaving empty area, making routing and implementation difficult, and causing additional circuit delay.

PPA Penalties and Program Risk

POWER:
TMR’d circuits consume more than 4× the power of commercial designs due to triplication.

Performance:
Voter logic and additional routing adds delay, resulting in >2× slowdown.

Area:
Triplication plus voter logic requires >4× area (and often much more due to the node-separation requirements)

Radiation Hardness:
Dense TMR provides only 5–6× improvement over commercial cells. Spatial redundancy to achieve higher radiation hardness further increases the already large area penalty and design complexity.

Because of these steep penalties, TMR cannot realistically be applied everywhere in a large chip. Some areas inevitably remain unprotected. If a critical area fails radiation testing late in development, the chip must be redesigned, reverified, and retested. With today’s long radiation testing backlogs, this can add two years or more to program schedules.

Design Complexity

TMR requires the chip designers to implement redundancy and voting logic everywhere in their design.

This adds verification overhead, slows design cycles, and diverts resources from higher-level architectural innovation.

LEAP Standard Cell Library: A Paradigm Shift

LEAP (Layout Design through Error Aware Positioning) provides inherently hardened standard cells that eliminate the need for TMR on FinFET and GAA process nodes.

Radiation Robustness:

LEAP cells are 10⁵× harder than equivalent commercial logic cells, orders of magnitude stronger than dense TMR’s 5–6× improvement.

Uniform Application Across the Chip:

Because LEAP cells impose only modest PPA penalties, they can be used everywhere in a design. This eliminates the selective “patchwork” protection of TMR and reduces the risk of late-discovered weak points during radiation testing.

Improved PPA Balance:

Power: As low as a 10–20% increase compared to commercial cells.

Performance: As low as a 10–20% delay penalty compared to commercial cells. 

Area: Larger than a commercial cell, but significantly less than TMR’s >4× expansion.

Design Simplicity:

Engineers can directly substitute LEAP cells into designs, skipping complex triplication schemes. This accelerates development and verification, allowing focus on system-level innovation.

Sec 4

Comparative Analysis: TMR vs. LEAP

Metric	TMR with Commercial Cells	LEAP Hardened Cells
Radiation Hardness	5–6× harder than commercial with standard dense spatial redundancy	10⁵× harder than commercial
Power	4× penalty to commercial	+10–20% over commercial
Performance	2× penalty to commercial	+10–20% over commercial
Area	4× penalty to commercial	1.5–2.7× penalty to commercial
Design Complexity	High (triplication + voters)	Low (drop-in cell replacement)
Program Risk	High (cannot harden entire chip, risk of redesign adding ~2 years)	Low (usable across full chip, reducing risk of late failures)
Scalability	Poor (statistical & proximity failures)	Strong (intrinsically hardened)

005 Rad-Hard

HPSC Case Example

A government agency’s development of a High Performance Space Computer illustrates the risks of relying on traditional TMR:

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The possibility of discovering unprotected critical circuits during late-stage radiation testing meant facing redesigns, reverification, and retesting, potentially adding two years to the program due to testing backlogs.

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Conclusion

Sec 6

Conclusion

A government agency’s HPSC program highlights a broader lesson for the space industry: as semiconductor technologies advance, traditional TMR-based RHBD is no longer sufficient. The penalties in power, performance, area, and design complexity make it unsustainable for next-generation, high-performance space processors

JRC’s LEAP Standard Cell Library provides a transformative alternative. By embedding radiation hardness into the standard cells themselves, LEAP allows designers to deliver advanced processing performance in radiation environments without the crippling penalties of TMR. With minimal PPA overhead and the ability to harden the entire chip, LEAP not only improves reliability but also dramatically lowers program risk.